As part of AMD’s Financial Analyst Day 2022, AMD unveiled an updated server CPU roadmap up to and including 2024. Nestled within AMD’s latest server roadmap, it highlighted the Siena series, much like the Genoa (due Q4 2022), Bergamo (Due 1H 2023), and the Siena family from its 4th gen EPYC series are expected to land sometime in 2023. While roadmaps only give a glimpse of what is expected, they are used internally to plot and plan specific product groups and keep them on track for release.
The AMD Siena family of 4th generation EYPC processors are slightly different from Genoa and Genoa-X because Siena is primarily designed for the Edge and Telecommunication industries. Siena will feature up to 64 Zen 4 cores, and AMD states it will be a lower-cost platform in comparison to Genoa, Genoa-X, and Bergamo, all of which will be based on AMD’s Zen 4 core architecture and TSMC’s 5 nm and the even more highly optimized 4 nm process node.
AMD’s Siena family of EPYC 7004 products will likely be compatible with the SP5 platform that launches alongside Genoa in Q4 2022. SP5 features support twelve channels of DDR5 memory and PCIe 5.0 lanes, but it is unclear how AMD intends to package its Siena family in terms of die layout or whether it will feature a cut-down feature set to make it more affordable.
SP5 features support twelve channels of DDR5 memory and PCIe 5.0 lanes, but it is unclear how AMD intends to package its Siena family in terms of die layout or whether it will feature a cut-down feature set to make it more affordable. (From the Anandtech article.)
Are there “cut-downs” that make sense for Siena? One possible choice is to use Raphael silicon possibly with uncore that includes fewer (LP)DDR5 memory channels, some HBM memory in the package, and maybe more PCIx5 lanes. Also, crypto accelerators would be a good idea. At least the usual AES lengths, (128, 192 and 256 bits) and an arbitrary arithmetic capability for RSA.
If AMD makes a new CPU chiplet, what could they do to reduce chiplet area without harming suitability for edge work? The first is to reduce the number of floating-point registers, and perhaps eliminate some of the SIMD extensions. You don’t expect edge CPUs to do heavy floating-point math. I wouldn’t eliminate 64-bit floating-point arithmetic, I probably could be convinced to take out the old x87 ISA.*
Anything else? We could probably argue the number of CPU cores, and whether or not they have multithreading. I expect AMD to offer several core and clock options, and you choose the one that matches your use case.
I might be one of fewer than a dozen people who use the x87 stuff. It is so convenient to have CPU support for 80-bit floats when validating floating-point libraries. But even if the libraries were used on a Siena processor, there is no need to validate overflow and rounding on an operational edge chip.