Lunar Lake Samples showing up - no hyperthreading


Per a screenshot of Windows Task Manager posted on Zihu (via HXL), an A1 LNL sample was running at the base and boost clocks of 1.8 GHz and 2.78 GHz respectively. Additionally, the chip seemingly had 8 cores and 8 threads which aligns with a big leak that dropped in November. The mention of only 8 threads is quite important since multiple rumors have alleged that Intel is ditching Hyperthreading.

Moving on, we can also see from the screenshot that the LNL chip has 832 KB of L1, 14 MB of L2, and 12 MB of L3 cache. Explaining the cache situation of Lunar Lake, Bionic_Squash on X explained that, in addition to 48 KB of L0 and an 8 MB SLC, LNL contains:

  • 256 KB and 96 KB of L1 cache for every P and E core, respectively.
  • 2.5 MB of L2 per P-core and 4 MB of L2 for the E-core cluster.
  • No L3 cache for the E cores while the P cores get 3 MB each.

This makes a lot of sense to me for a few reasons. Many of the difficult viruses we have seen in the past attack the hyperthreading capability.

Intel has said they can fit three E-cores in the same space as one P-core. For heavily threaded and power constrained applications E-cores would win over hyperthreaded P-cores.

I suspect getting rid of hyperthreading makes the P-core a little simpler and faster.
I know this goes in the opposite direction of what many predicted, which was a 4-way SMT but Big/little changes the calculus a bit.
Alan

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This makes a lot of sense to me for a few reasons. Many of the difficult viruses we have seen in the past attack the hyperthreading capability.

Excellent point. Too much pain and too many intractable issues.

I suspect getting rid of hyperthreading makes the P-core a little simpler and faster.
I know this goes in the opposite direction of what many predicted, which was a 4-way SMT but Big/little changes the calculus a bit.

I think I remember there being rumors that AMD would use 4-way SMT which didn’t appear in the end, I wonder if your security concern was one reason why. Also, as you suggest, maybe simpler is faster, and easier to shrink into the 5c/6c type configurations.