Nvidia: Improved AI for microchip circuit design


" Nvidia chief scientist Bill Dally said the work is important because chip manufacturing improvements are slowing with per-transistor costs in new generations of chip manufacturing technology now higher than previous generations.

That goes against the famous prediction by Intel Corp (INTC.O) co-founder Gordon Moore that chips would always get cheaper and faster.

“You’re no longer actually getting an economy from that scaling,” Dally said. “To continue to move forward and to deliver more value to customers, we can’t get it from cheaper transistors. We have to get it by being more clever on the design.”"


Just to pick a very large nit, Moore made the prediction in a 1965 interview in Electronics Magazine, and said it was probably valid through 1975.

The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.

It was others who stretched (and even named) “Moore’s Law”, not him. The time scale dilated to 18-months from his original one year, but otherwise it has held up remarkably well, even as people predicted that it was getting near-impossible etching ever more transistors closer together on a wafer.


Just curious, is the AI program named Skynet?

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Some 20 years ago the talk was designed dna forming chips. Far out there man. Any hope for a bio chip?

Jensen has claimed Moore’s Law is dead. And he is probably right. I heard that at least 7 years ago while I was at Oracle (on SPARC), so maybe he is just late and cautious in saying this. ;). But he is correct in that AI is going to help chip design. What that article is talking about specifically is layout. Jensen has also recently talked about our supercomputers being used to help design the mask sets to use the quantum property of interference to make geometries smaller than the wavelength of light being used in lithography. And to make these masks MUCH faster and cheaper.

Exciting times!



What is the “mask”?

I’ll try a quick explanation. Remember the transparancies our teachers used in school to teach us with? A transparent sheet that you wrote on with black marker, shone light through a lens and project it on a screen. The ink blocks light in some places. Chips are built in layers, and each layer is defined by a mask exactly like this. What usually happens is a photoresist resin is put down and then light is shown through a mask. The resin hardens with the light and the rest is washed away, leaving a pattern behind. Then something can be done, like deposit metals or impurities where the mask was not hardened and washed away. Then literally wash rinse repeat. Complex chips can have 20+ layers. The masks must be incredibly precise.

We currently use light that is barely visible. But wavelength matters. The geometries you are trying to project cannot be smaller than the wavelength of light used for reasons of physics. There was concern we’d have to go extreme ultra violet. This is a problem, because not everything is opaque (like the ink) at higher frequencies, making the mask useless. What Jensen is doing is using computational lithography to make use of interference patterns to etch geometries smaller than the wavelength used. We can use 13nm light to make masks for 3nm geometries. That is amazing.

And people wonder why it’s useful to know things like optics, waves, and quantum mechanics. :slight_smile:



And I have had a smattering of optics, waves, and quantum studies.

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And keep in mind, none of this is done by Nvidia. Nvidia designs chips and has them made at a foundry like Taiwan Semiconductors. Of course they must be knowledgeable about what the foundry can do in terms of line width, etc.


Anyone designing chips is also going to do the layout, the physical design. That is not done by the fab. So, yes, Nvidia IS doing things like using AI to do layout and physical design, on their chips. Also, our software and our hardware IS being used to create these mask sets in less time at less expense. And not just our masks, but anyone’s masks used by that fab house.

Edit for more detail about chip layout. There are layout tools and they have been around a long time that will take your design and place the transistors, the wires, etc. They do a reasonable job and are necessary when chips have billions of transistors. (The Oracle SPARC M7 I worked on had 10B transistors and this was 2015). However critical parts of the logic still have manual intervention, if not outright manual place and layout. This might be to meet critical timing needs, totally minimize area, or have the most impact for power consumption. Also tool-routed portions can be manually adjusted as well, to make the tool do its work in a slightly different way. The tool still does the work, but is guided by human intervention.

What we are doing at Nvidia is using ML based tools to do this layout better than existing tools do. Very cool stuff.


I read somewhere that one of the most difficult parts is not making the mask or even applying it, it’s getting all the masks to align so they can pass the electrons back and forth. It’s like plumbing, layer #17 has to pass electrons to layer #16, but both were built from horizontal masks, so there has to be a “connection point” (or many) which line up vertically so the data can move through the chip vertically, rather than have to exit horizontally, find an elevator up, then re-enter on a different level.

I don’t know if all that’s true, but it painted a good picture for me to understand just how precise all of this needs to be. Designing and making a single layer was relatively easy (!) this article said, it’s like an architect’s drawing board. It’s making all the layers work together that’s the trick. True? No? Dunno.

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More here on the latest GTC from Nvidia:

It’s long, but there are sections that talk a lot about Moore’s Law, mask costs, computational lithography, etc. Good stuff at the very beginning, and at 22:30.

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The chips get tested before they get connected and packaged. Misalignment of masks causes defective chips. Ie low yield.

Yes, high precision placement throughout is essential.