TSMC 3nm ahead of schedule


The Taiwan Semiconductor Manufacturing Company (TSMC) has reported impressive yields for its next-generation chip manufacturing technology. Dubbed as the N3e, this technology is an upgrade over TSMC’s first iteration of the N3 node, which expects to shrink down some transistor dimensions to as low as 3-nanometer. Today’s report comes courtesy of Morgan Stanley, who has released a new research report titled “Production yield of N3e is higher than expected; reiterate OW” and shared on Twitter.

TSMC Moves Forward N3E Production By A Full Quarter Believes Investment Bank Morgan Stanley
A snippet of the report has been shared on the social media platform Twitter by the user going by the name Retired Engineer. This snipped cites Morgan Stanley’s checks with equipment vendors to suggest that TSMC might “freeze” its design parameters for the N3E node as soon as by the end of this month. This is due to better than expected yield for the process and it indicates that volume production for the process, which is one of the final stages before a chip node enters mass production, might start by the second quarter of next year.

The snippet, shared by the Twitter user, states that:

N3e production yield improves; schedule being pulled in: Our recent checks with equipment vendors suggest that TSMC may freeze the N3e process flow sooner - by the end of this March. This means that volume production of N3e may start in 2Q23, around a quarter ahead of the original schedule of 3Q23. The test production yield is much higher for N3e than N3b. Our checks suggest that the logic density of N3e is only ~8% less than that of the original N3 by cutting four EUV layers, yet it’s still 60% denser than 5nm. All this makes N3e a competitive node for TSMC in terms of cost and timing.

The snippet from Morgan Stanley’s report shared by @chiakokhua on Twitter.
Morgan Stanley’s news comes after sources in the Taiwanese press had speculated that TSMC is facing troubles with its 3nm yield. In the semiconductor industry, the yield of a process is defined as the number of chips that pass quality control checks on a single wafer, and the higher the percentage, the more mature a process is. Fabs such as TSMC often take their time to perfect this metric as it deepens their customer relationships and improves the quality of their products.

It also mentions the existence of an N3b node, which had previously been speculated to have been introduced as a stop-gap measure by TSMC due to poor yields. While the earlier reports had speculated that TSMC’s customers had chosen to stick with the relatively mature 5nm node due to the alleged yield defects, whether this still remains to be the case is uncertain.


Let me respond to this post first, and assume that a decent response to other posts will have to wait for tomorrow. This is not TSMC’s 3 nm process ahead of schedule, it is their second 3 nm process, due in mid-2023. Based on what I have heard, even though this process is not quite as dense as the original 3 nm process, the higher yields will cause many customers to skip the first 3 nm process. Apple? AMD? nVidia? Intel? Qualcomm? Beyond these, there is probably no reason to use TSMC’s first 3 nm process. My guess? Apple will, AMD and nVidia will skip N3b (for N3e) due to product timing issues. (AMD will use 5 nm for Zen 4, and nVidia for the Ada Lovelace 40xx series.)

One last detail. Volume production for N3e is apparently now planned for 2Q2023. There will be risk production prior to that. So don’t be surprised if N3e samples show up late this year. But any 3 nm products this year will be N3b.