Hi Nilvest & others - - I think you’re somewhat correct in that I maybe jumped to a “dangerous and risky conclusion”. But please read on. Absolutely, memory ICs have to be one of the most cost sensitive things ever made (despite the ridiculously high level of capital and technology that goes into making them!). What drove me to my conclusion is the fact that Aehr can now provide fully automated wafer-carousel-in to wafer-carousel-out handling, driving stress testing volumes up and per chip costs down. This new automation just happened last quarter, from what I read below in Gayn’s conf call from 4q23 - -
"Alternatively, the Auto Aligner can be configured to dock directly to the front of a FOX-XP system such that all material handling and WaferPak movement is done 100% hands free up to and including fully lights out operation. As capacity and volume forecasts grow, eliminating all manual interfaces for automated handling can become critical to our customers.
The added automation capability of our new Aligner gives our wafer level test and burn-in offering even greater value and opened several significant incremental markets to Aehr such as high volume processors and chipsets with integrated photonics transceivers, flash and ultimately DRAM memories and higher-mix devices requiring extremely high reliability and 100% burn-in such as automotive microcontrollers and sensors."
I think this is very new info to the memory chip makers - and they’re not quite sure what to make of it yet. So we may both be a bit right. Let me also cite a ques I asked chatGPT about this, and its answer - -
With reference to your prior answer, you state that “Automated robotics and handling systems are used to load packaged ICs into burn-in chambers and retrieve them after the burn-in process is complete.” Does it make more sense, that is, does it result in lower stress testing cost per memory IC, if the manufacturer performs the stress testing when the memory IC is in wafer form instead of in packaged part form?
Performing stress testing when the memory IC is in wafer form can indeed result in lower stress testing costs per memory IC compared to testing the packaged parts. This is primarily because testing at the wafer level allows for testing multiple ICs simultaneously, and it can be more cost-effective in terms of equipment, handling, and test time. Here are some reasons why wafer-level testing can be cost-effective:
Parallel Testing: Wafers can contain hundreds or even thousands of individual memory ICs. Wafer-level testing allows all of these devices to be tested in parallel using specialized testing equipment. This high parallelism reduces the overall test time and increases throughput, making it more cost-effective per IC tested.
Reduced Handling and Packaging Costs: Wafer-level testing eliminates the need for packaging individual ICs before testing. Packaging can be a significant cost factor, especially for high-density memory devices. Testing in wafer form reduces the need for expensive packaging materials and labor-intensive assembly processes.
Lower Equipment Costs: Testing equipment designed for wafer-level testing can be more cost-effective than equipment used for testing packaged parts. Wafer-level testing equipment is optimized for testing multiple devices simultaneously, which can result in a lower cost per device tested.
Early Defect Detection: Wafer-level testing helps identify and eliminate faulty or low-quality dies early in the manufacturing process. This reduces the cost of packaging and assembling potentially defective ICs, improving overall yield and reducing waste.
Improved Data Analysis: With wafer-level testing, manufacturers can gather data on the performance and characteristics of individual dies on the wafer. This data can be valuable for process optimization and yield improvement efforts.
However, it’s essential to consider the trade-offs and limitations of wafer-level testing:
Limited to Early Screening: Wafer-level testing primarily focuses on early defect detection and basic functionality testing. Some stress tests, such as extended burn-in, may still need to be performed at the packaged part level to ensure long-term reliability.
Additional Handling Steps: Transitioning from wafer-level testing to packaging and then to final testing adds additional handling steps, which may introduce some risk. It’s important to ensure that devices are not damaged during these transitions.
Cost of Wafer-Level Testing Equipment: While wafer-level testing can be cost-effective per device tested, the initial investment in wafer-level testing equipment can be significant. Manufacturers need to weigh this investment against the potential long-term savings.
In conclusion, wafer-level testing can be a cost-effective approach for stress testing memory ICs, particularly for early defect detection and basic functionality testing. However, it may not replace all testing at the packaged part level, especially for tests related to long-term reliability and performance. Manufacturers typically use a combination of wafer-level and packaged part testing to ensure the highest quality and reliability of their memory ICs while optimizing production costs."
One thing I see from this response is that, because chatGPT 3.5 only had data from 2021 and earlier, it was not aware of the newer (automated handler) developments at Aehr. It also seems to assume that the reliability testing (removing early life failures) can’t be done at wafer level.
We’ll see if the memory guys come along eventually - I agree, I don’t think it’s a given, and Gayn has said that he sees the possibility for NAND flash memory before DRAM (and I don’t know why).
Another thing that has me thinking memory market for Aehr is the rapid movement to many types of very, very specialized packaging of ICs for the AI and datacenter markets. Here, as I read it, makers are stacking memory ICs on top of other memory ICs, and then dropping the stack onto a specialized substrate which connects the memory stack to the processor to the comms IC, etc. To build one “package” like this seems to require that EVERY chip has been put thru burn-in stress testing to eliminate any chance of early mortality.
Best - - JK