Aehr--Memory Angle?

The part of the Aehr call that had me the most interested, but that I understand the least, was the question and answer about memory at the end. It went like this:

Larry Chlebina: As you say, the XP was developed initially for memory, the lack of the automation held it back. Now that it’s fully accepted and it’s in the marketplace, when are you going to get an evaluation tool to our big U.S. memory maker that’s planning on building several fabs in the U.S.

Gayn Erickson: As we’ve alluded to, and we are serious about it, we are actively pursuing the memory space again. We have had conversations and design reviews, not with everybody, but some of the folks that are candidly closer proximity, but not only on it, and that continues on, including with some meetings over the next few weeks. It’s a little awkward, but shareholders need to sort of understand. We actually have financial bonuses tied to every executive and its staff to get into memory. That includes me and every one of my staff members. [emphasis mine] They are multiyear plans, but we’re always getting in the memory. That has been my passion. That’s what the tester was originally designed for, and we’re not giving up.

Larry Chlebina: Well, you’re the memory guys. So you’re going to make it happen.

That every executive in the company and their staff are financially incentivized to “get into memory” seems important. It also seems like a huge increase to the TAM.

Can anyone speak to what this means related to Aehr’s current products? Would memory chips (assuming that’s what they’re talking about) need the same level of testing or can many more companies do this easily? Who is/are the big fish that Aehr is incentivizing their top people to go after in the memory space? And who is “our big U.S. memory maker.” Intel?



Memory is the holy grail for AEHR and what DARPA gave AEHR the contract for long ago. To date, however, no memory customers. This is always considered few years down the road at least, if ever. But it is the jackpot for AEHR if it takes off.

AEHR hopes that AEHR burn in in one section of a fab will leak into other sections of the fab, thus dispersing the technology. For now though it is another market, larger market than them all but one that may be at the end of the decade or further unless interest unexpectedly develops. AEHR would love through their interactions to plant the bug so that someone at a potential customer runs with it sooner than later.

It has been long thought for decades that volume burn in of memory has been a national priority for future tech to dominate. As to why, I’m not so versed in it. May dig into that tonight. But for now that is an investor who has dreams of avarice and he’d like Gayn to give him some good news in regard. For now it is a potential but not something to plan for any time soon.


If it is burn-in for DRAM the major US memory maker he is referring to has to be Micron


JabbokRiver and others - I too have been carefully following Gayn’s commnets about silicon memory - - I might be able to add some light to the topic of Aehr’s future potential to begin wafer-level burn-in and test for silicon memory ICs and possibly other high volume silicon integrated circuits. From my past experience (25 yrs in various roles in IC manufacturing w/various companies), and reading a bit into Gayn’s comments in the current and just prior earnings call, I glean the following - -

  1. The shift underway to improve data transfer speed is driving the need to complex packaging, housing a few to very many chips in ONE package. Since the failure rate of the final package is the product of the failure rate of each individual chip in that package, all of the chips must be stress tested (burned-in under high temp/high voltage conditions) so that each and every chip gets past its early life failure potential. This means that Aehr might see customers wanting to do wafer level stress testing of logic ICs, processor ICs, etc and not just memory - and Gayn has spoken to this tangentially several times.
  2. Memory ICs are routinely stress tested now (again, burned-in for 12 or more hours under high temp/high voltage conds. to eliminate early life failures that would be expected from a non-stress tested IC over its about 1st 3 months of usage). With a little help from chatGPT - “Yes, most manufacturers of silicon memory Integrated Circuits (ICs) routinely perform burn-in stress testing before shipping out the memory ICs. Burn-in testing is a standard and essential part of the quality assurance process in semiconductor manufacturing. It helps identify and eliminate early failures in the ICs, ensuring their reliability and performance over their intended lifespan.” So the KEY issue re Aehr is whether they can convince the memory makers that their automated/high volume/wafer-level testing results in higher throughput, lower-cost stress testing per chip than the method that the memory maker is currently using to do his stress test today. Personally, I don’t think there is any contest. Individual packaged-part memory testing is slow and costly because the automation is limited. If one could test hundreds-to-thousands of chips at once (ie whole wafer test), and multiple wafers at one time, and in an automated wafer handling manner, ie Aehr’s way, then the cost of stress testing per memory ICs ought to be dramatically lower. This is why I think Gayn said he was smiling (from prior 4q23 CC) - -

"Larry Chlebina

Yeah, I’m there. Gayn, you started to answer my question, my primary question, when you might have an evaluation tool to since you have a fully automated machine now, it seems like one of these memory guys might be interested in evaluating it for future fabs?

Gayn Erickson

I agree. If I were a memory guy, I would want to evaluate our tool as well. So that is something that is important to us. I often tell people, be careful, don’t assume, we’re going to be having revenue anytime immediately, but it is absolutely something that we are that we’re working towards.

And for sure, our new WaferPak automated Aligner is a key piece of that. And we did get feedback from multiple memory companies on that configuration and its capability. I will share that with you. So I’m very for people that know me or have seen the picture of me smiling next to it before we shipped the first one. It’s a passionate project for me and this team is very, very proud of that. So I’ll leave it at that, Larry."

So, in short sum, maybe there’s opportunities for addn’tl sales for Aehr for testing the silicon chips that go into multi-chip modules and for testing silicon memory chips - and that’s a very, very large number of wafers.
Best to all - - JK


Wow…VERY helpful, @jkemps!

I added to my Aehr position on the selloff today, and it was already my largest. It does seem like Aehr is the only game in town if you want to do burn-in testing at scale.



This is a bit older but Kingston testing 500 dram chips at a time in their proprietary internally created burn in tester:

Don’t know where AEHR’s tester would fall in the scheme of things in comparison.

Here is another one but for smaller volume: Despatch Computer Memory Burn-in Oven | Case Study

Here is a recent article that makes the point that AI chips are particularly difficult to test. These “probes” mentioned are used in standard testing devices. Something AEHR doesn’t have in their machines. This may be a place where AEHR can fix some pain points:

I’m sure many more articles out there but a start n


thats a very dangerous and risky conclusion…

memory is relatively mature market and extremely sensitive to cost… so if there was a better way they were convinced off, they would have adapted very fast… because its really the fastest rat race in technology… these guys go through crazy capex cycles on fab, if a burn in tester would get them few % more, they would do it in a hear beat…

the fact that AEHR is not even getting their first serious customer adoption with memory tells you that memory guys have at-least equivalent or better way to address this…

yeah, that seems more like it… ofcourse the challenge of burn-in memory operating at low single digit voltage (3V or lower down to may be 0.7V) is much different than SiC or GaN for power semiconductors… and may be, just may be, they fact is that memory guys have all taken care of this problem well and AEHR does not have much to add to

With the same token, I am not sure of silicon photonics is really that promising for AEHR… because this is not power semiconductor… it is high speed data at again single digit volt operation… or may be a fraction of a volt… that dilutes AEHR differentiation…

I do not want to sound like AEHR bear, they are solving major bottleneck and clearly one company (88% revenue this quarter) is building their operation around AEHR which is a big proof, I think this capex oriented business is much lumpy and in today’s market (with interest rate regime), downside risk is much higher on missing one or two quarters than upside at the current valuation. Just think about this - next quarter, if the 88% customer buys nothing… just for one quarter because they are setting things up and going on with production, capex is done… everyone else together can barely cover up short fall to be flat, forget growth for q/q.

I would not short this but its too much of a story based valuation even after yesterday’s drop.


It isn’t just memory manufacturers. Microprocessor manufacturers can boot up and run test software on microprocessor chips while they are still colocated together on a wafer. They do this as part of the burn in process. Think of a “bed of nails”. The robot places the wafer (size of old 33 LP record album) onto the bed of nails. The “nails” have power and data connections that connect to little spots on the wafer. They provide power and data signals to start the test and measure the results.

I don’t know what AEHR would bring to that table that hasn’t already been there for a decade. They did bring something to the high power chip world.


nilvest, you clearly know far more than I do about this market. Given your comment about silicon photonics not being that promissing for AEHR, would you comment on the following excerpt from the earnings call? Do you think the CEO is wrong here?

"Our FOX wafer level test and burn-in solution with our proprietary WaferPak full wafer contactors are a great fit for the silicon photonics semiconductor market. These next-generation silicon photonics-based integrated circuits can require up to 2x to 4x as much power for full wafer test burn-in and stabilization. And our FOX new production system configuration, which can be used to test and burn in these new optical I/O devices expands the market opportunity of the FOX-XP system even further. The power and functionality of lasers used to transmit data are critically important to the performance of the communication channel and Aehr Solutions not only weed out early life failures but also improve the performance of the device to what photonics industry refers to a stabilization.

During the first day or two of normal operation, the laser output characteristics change in an exponentially decaying manner and must be stabilized until the decaying stops before the final product can be tuned to meet its performance specification. Aehr can do this across an entire way for a fully integrated photonics integrated circuits with embedded or attached laser emitters. These fully integrated circuits with lasers are reportedly the highest performance and level of integration possible, which is optimal for integrating into a package along with a microprocessor, graphics processor or artificial intelligence processor for optical chip-to-chip communication. Aehr currently has six customers using our systems for production test of silicon photonics devices."


GAAP net income is still expected to grow 92% this FY to $28m. AEHR enterprise value after the drop yesterday is ~$1B. So people buying now are paying ~36x for earnings that are almost doubling. The valuation is no longer stretched unless you think they are not going to hit their guidance or the growth is going to get crushed next year.



I’ve spent the better part of the day trying to get a better understanding of Aehr’s competitors. It’s been a very frustrating exercise.

First off, semiconductor burn in testing is not just one type of test, there are numerous very different tests that are all referred to as burn in. So I’ve visited several different websites (Adventest, Teradyne, etc.) only to find that none of the burn in tests were even remotely similar to the kind of testing provided by Aehr’s test equipment. I won’t fill this post with descriptions of these different tests, if you really want to know, go waste your time (or maybe I should say, become needlessly informed) like I did.

Anyway, I’m now under the impression (maybe incorrectly, but I’ve not found much information to contradict it) that Aehr’s biggest competitors are the fab foundries that have developed internal equipment and processes to test their own products. Much like Tinker noted about Kingston performing their own testing of 500 chips at a time.

I believe (maybe incorrectly) that Aehr might still get a wedge into this market. Aehr does not test chips, they test wafers that come out of the lithography machines. Chips are way down the line after wafers have been cut apart and the etched material gets assembled with contacts, a casing, packaging and I’m not sure what else. The opportunity to not even make a bunch of chips that fail in later testing might sound appealing to a memory chip maker. Of course, the assembled chips still need to be tested.

But Aehr does not provide functional testing. Aehr would eliminate a considerable number of failures, most importantly those that are prone to fail in the first year after being sold to the end user. The manufacturer still needs to test the assembled chip prior packaging and shipment to insure that it actually works. Maybe, probably Aehr hasn’t been able to convince any memory chip maker that Aehr’s burn in testing will save them any money. I don’t know. I’m speculating.

In any case, I’ve not been able to find another vendor that provides the kind of burn in test equipment that Aehr provides. This might be a function of my ignorance of the industry. But one thing’s for sure. You can’t just Google “microprocessor burn in test equipment supplier” and expect to find any company other than Aehr that provides similar burn in test equipment. Aehr appears to have a monopoly in this niche.

So when it comes to high power SiC chips, I think Aehr has a lock on it. As other BEV makers ramp up, so will demand for these chips. And there are several non-automotive applications which require pretty much fault free SiC chips. As for the potential photonics needs for GaN chips, I tend to trust that Gayn knows this industry extremely well. I don’t think he’s just blowing smoke.

So IMO Aehr has a bright future. But we don’t have a lot of insight as to when that future might arrive and how fast it will build. In other words, my enthusiasm for this investment opportunity might be somewhat premature. But maybe not. I’m willing to at least see what next quarter brings, but I might trim Aehr a bit in order to free up some cash to invest elsewhere.


Hi Nilvest & others - - I think you’re somewhat correct in that I maybe jumped to a “dangerous and risky conclusion”. But please read on. Absolutely, memory ICs have to be one of the most cost sensitive things ever made (despite the ridiculously high level of capital and technology that goes into making them!). What drove me to my conclusion is the fact that Aehr can now provide fully automated wafer-carousel-in to wafer-carousel-out handling, driving stress testing volumes up and per chip costs down. This new automation just happened last quarter, from what I read below in Gayn’s conf call from 4q23 - -

"Alternatively, the Auto Aligner can be configured to dock directly to the front of a FOX-XP system such that all material handling and WaferPak movement is done 100% hands free up to and including fully lights out operation. As capacity and volume forecasts grow, eliminating all manual interfaces for automated handling can become critical to our customers.

The added automation capability of our new Aligner gives our wafer level test and burn-in offering even greater value and opened several significant incremental markets to Aehr such as high volume processors and chipsets with integrated photonics transceivers, flash and ultimately DRAM memories and higher-mix devices requiring extremely high reliability and 100% burn-in such as automotive microcontrollers and sensors."

I think this is very new info to the memory chip makers - and they’re not quite sure what to make of it yet. So we may both be a bit right. Let me also cite a ques I asked chatGPT about this, and its answer - -

With reference to your prior answer, you state that “Automated robotics and handling systems are used to load packaged ICs into burn-in chambers and retrieve them after the burn-in process is complete.” Does it make more sense, that is, does it result in lower stress testing cost per memory IC, if the manufacturer performs the stress testing when the memory IC is in wafer form instead of in packaged part form?
Performing stress testing when the memory IC is in wafer form can indeed result in lower stress testing costs per memory IC compared to testing the packaged parts. This is primarily because testing at the wafer level allows for testing multiple ICs simultaneously, and it can be more cost-effective in terms of equipment, handling, and test time. Here are some reasons why wafer-level testing can be cost-effective:

Parallel Testing: Wafers can contain hundreds or even thousands of individual memory ICs. Wafer-level testing allows all of these devices to be tested in parallel using specialized testing equipment. This high parallelism reduces the overall test time and increases throughput, making it more cost-effective per IC tested.

Reduced Handling and Packaging Costs: Wafer-level testing eliminates the need for packaging individual ICs before testing. Packaging can be a significant cost factor, especially for high-density memory devices. Testing in wafer form reduces the need for expensive packaging materials and labor-intensive assembly processes.

Lower Equipment Costs: Testing equipment designed for wafer-level testing can be more cost-effective than equipment used for testing packaged parts. Wafer-level testing equipment is optimized for testing multiple devices simultaneously, which can result in a lower cost per device tested.

Early Defect Detection: Wafer-level testing helps identify and eliminate faulty or low-quality dies early in the manufacturing process. This reduces the cost of packaging and assembling potentially defective ICs, improving overall yield and reducing waste.

Improved Data Analysis: With wafer-level testing, manufacturers can gather data on the performance and characteristics of individual dies on the wafer. This data can be valuable for process optimization and yield improvement efforts.

However, it’s essential to consider the trade-offs and limitations of wafer-level testing:

Limited to Early Screening: Wafer-level testing primarily focuses on early defect detection and basic functionality testing. Some stress tests, such as extended burn-in, may still need to be performed at the packaged part level to ensure long-term reliability.

Additional Handling Steps: Transitioning from wafer-level testing to packaging and then to final testing adds additional handling steps, which may introduce some risk. It’s important to ensure that devices are not damaged during these transitions.

Cost of Wafer-Level Testing Equipment: While wafer-level testing can be cost-effective per device tested, the initial investment in wafer-level testing equipment can be significant. Manufacturers need to weigh this investment against the potential long-term savings.

In conclusion, wafer-level testing can be a cost-effective approach for stress testing memory ICs, particularly for early defect detection and basic functionality testing. However, it may not replace all testing at the packaged part level, especially for tests related to long-term reliability and performance. Manufacturers typically use a combination of wafer-level and packaged part testing to ensure the highest quality and reliability of their memory ICs while optimizing production costs."

One thing I see from this response is that, because chatGPT 3.5 only had data from 2021 and earlier, it was not aware of the newer (automated handler) developments at Aehr. It also seems to assume that the reliability testing (removing early life failures) can’t be done at wafer level.

We’ll see if the memory guys come along eventually - I agree, I don’t think it’s a given, and Gayn has said that he sees the possibility for NAND flash memory before DRAM (and I don’t know why).

Another thing that has me thinking memory market for Aehr is the rapid movement to many types of very, very specialized packaging of ICs for the AI and datacenter markets. Here, as I read it, makers are stacking memory ICs on top of other memory ICs, and then dropping the stack onto a specialized substrate which connects the memory stack to the processor to the comms IC, etc. To build one “package” like this seems to require that EVERY chip has been put thru burn-in stress testing to eliminate any chance of early mortality.
Best - - JK


Sorry, I do not want to come across highly knowledgeable because I am not… I am in semi industry but dont have enough exposure to this side of the industry…

I am just trying to challenge based on some basics that I understand.

My simple understanding is AEHR is a tiny company around for decade + … that means its solving something new… not really something thats core to semi industry…

the new here is very high demand for power electronics driven by EVs… and speciality they have is around avoiding damage to chips while wafer burn in at high voltage… this specific requirement makes sense for SiC and also GaN (only used in power electronics GaN also used for very low volume, high speciality communication… but that is not the subject here)

And this particular requirement “should” not exist in silicon photonics… as purpose of silicon photonics is to transmit much higher speed data at a much lower power consumption (compared to traditional method)… this is not a device delivering power, this is a device meant to reduce power consumption… and usually we are talking about few watts here… not few Kilo Watts that SiC needs to deliver…

AEHR may have added all other bells and whistles (e.g. automating the flow…) but those are not defensible by themselves… other people ought to / must be having these things as burn-in is not a new concept in semi industry… it is “high power devices burning at wafer scale” is new and AEHR has big lead. Everything else, take it with pinch of salt… may happen but dont pay up for that before it does happen…


Thanks for your reply nilvest. That makes sense. It may be worth checking out the CEO’s profile on Linked in. He’s an engineer by training and spent most of his long career in the testing business. Since prior to joining AEHR he held various roles at companies that sell memory testing equipment, I’d give him a benefit of doubt when it comes to testing memory chips. He may know what he’s talking about. On the recent call he mentioned that compensation of their sales and management teams is tied to them getting into the memory testing business so he’s putting where his mouth is as well.


@jkemps thanks for doing the research and providing your findings. You had better results than I. It was good idea to use AI assistance, I didn’t think of that. OTOH, you need to be careful with the answer. None of these new AI tools are 100% reliable. There were some things in the text you provided that simply didn’t make sense:

“Reduced Handling and Packaging Costs: Wafer-level testing eliminates the need for packaging individual ICs before testing. Packaging can be a significant cost factor, especially for high-density memory devices. Testing in wafer form reduces the need for expensive packaging materials and labor-intensive assembly processes.”

I guess it reduces the need by reducing the associated costs of packaging the ICs that fail the burn in test. But all the remaining ICs still need to be assembled and packaged. They are not usable after separating the wafer into individual ICs.

Later in the text, Chapt GP appears to acknowledge this:
“Early Defect Detection: Wafer-level testing helps identify and eliminate faulty or low-quality dies early in the manufacturing process. This reduces the cost of packaging and assembling potentially defective ICs, improving overall yield and reducing waste.”

And finally, there’s this:
“However, it may not replace all testing at the packaged part level, especially for tests related to long-term reliability and performance.”

That’s not quite accurate in that the burn in testing is specifically intended to eliminate faulty ICs related to long term reliability and performance. Part level testing is primarily functional testing intended to insure that the assembled and packaged IC actually does what it is intended to do.

I believe this is the primary inhibition to adopting Aehr’s wafer level testing. No matter how well wafer level testing screens out those chips subject to early mortality, in the end the fully assembled and packaged part still needs to be tested to insure that it functions properly. There are numerous manufacturing steps between etching the wafer and the fully assembled packaged part. This provides an opportunity for the IC to be damaged in some manner or for something else to go wrong during the ensuing processes.

So it becomes a trade off. If the wafer yield is already quite high, there’s not too much to be gained by weeding out the chips that will fail due to early mortality at this step in the manufacturing process so long as those faulty devices can be identified during part level testing.

I beg to differ a bit from @nilvest about the need for testing SiC being driven by high power requirements. It was (and still is) my understanding that the need for burn in testing of these devices is driven by the difficulty in producing SiC (and I assume) GaN at satisfactory purity levels. Unlike Si, the stuff is just very difficult to make. Impurities are randomly distributed in the raw material before the wafers are even made (few, if any IC manufacturers make their own wafers, they are purchased from a relatively small number of suppliers).

The random distribution of impurities that result in faulty end products is the driving factor for the economic payoff from early detection of faulty ICs. The yield of reliable ICs from each SiC wafer is much lower than that of a Si wafer. The largest SiC (and GaN) wafers available are 200mm while the industry (as I understand it) is moving to 300mm wafers for the production of Si ICs. Aehr’s equipment, as presently configured can handle any size wafer up to 300mm.

I’m pretty sure, but less than 100% confident, that the inhibition for using Aehr test equipment in the production of memory devices is due to the fact that there’s not a large economic benefit to be derived from early detection of faulty ICs due to impurities in the wafer material. Si wafers produced at the requisite purity level for IC manufacture is difficult, but not impossible (I resist the temptation to go off on a tangent about the manufacture of wafer material). Hence, there’s not much to be gained from wafer level testing for Si ICs in that individual part testing is still required regardless.

Conversely, the relatively low yield from SiC and GaN wafer material provides significant economic benefit from early detection of faulty ICs. It has much less to do with power handling requirements of the end application for the IC.


AEHR has multiple silicon photonics customers. AEHR indicates that Covid shutdown new orders but that in the last year or so interest has picked up. These are very large customers from Intel to Apple as examples.

No material money from silicon photonics yet. However they announced a sale on May of this year in silicon photonics: Aehr Receives Order for FOX-XP™ System for Production Wafer Level Burn-in of Next Generation Silicon Photonics Integrated Circuits

I forget the exact details but something to the effect that silicon photonics requires 3x
the burn in duration than SiC and at higher power levels. Making AEHR ideal for the job and why the interest. No one else can apparently do this. From AEHR anyways.

Also, a correction to the above conversation chain. Burn-in has little to do with amount of voltage running in the chip. It is about the material. Chips have a bathtub curve in regard to longetivity. Chips that can survive say the first 3 months (this number varies and may be even a year depending on context) will then go on and survive a long time. So burn in does not test the voltage that is expected to run through the chip but rather to pick out the bad chips that would fail in the first year or two by basically aging the chip.

This is somewhat counterintuitive because we want our new stuff new, but in computer chips you want the chip aged so you can tell if it will have a long life or not. A new chip simply is an unknown. But once a chip survives past a certain age then it will survive a long time.

With silicon photonics (1) you need to do the more rigorous testing as described above and (2) the chips are expensive when you combine it with the photonics. Thus essential to weed out the bad ones w degree of certainty that requires the longer and hotter testing times.

Here is the order from May 2023. Aehr Receives Order for FOX-XP™ System for Production Wafer Level Burn-in of Next Generation Silicon Photonics Integrated Circuits

So let’s not say there is no interest in AEHR on photonics. The interest exists but the photonics market is still quite small (about $1.2 billion in 2023 expected to grow to $7 billion or so by 2030 - but of course no one really knows).

As for DRAM AEHR may get into the conversation at some point but not hearing much of that happening now. Guess AEHR alluded to that in the earnings call. I’ll need to review that. But it is a more distant S curve and not something to expect until at least the latter part of this decade or beyond. Silicon photonics however is something that is happening now (was happening) but still largely in the early stages.


agree, thats why I say it may happen…

also, sure there is interest from silicon photonics customers… and even memory customers…

agreed, SiC and GaN burn-in needed sue to impurity… this is why its picking up with SiC gaining volumes…

please remember, mainstream (logic, memory and analog) semis have $100s of Bs of production running without AEHR equipment…

burn-in equipment itself is not high value… which is why no other stand alone company makes them…

my argument is simple - its high power burn-in at high capacity that is where AEHR adds value… they dominate it… they are only game in the town… and likely will remain so…
but that market may have a much lower ceiling for capex equipment and all these other things are not given.

Based on reality today, I have hard time envisioning AEHR revenue going above $200M / year anytime soon.

So for valuation, at 15 times TTM revenue, I would rather invest into recurring revenue software businesses (e.g. MNDY, ZS, CFLT…) with much higher confidence in their runway… even at a lower growth rate on TTM basis… its the forward growth rate for next 3 to 5 years where I think investing in AEHR is not attractive at current prices.


@CrazyCzech I can’t understand your notion that Aehr’s revenue won’t exceed $200M anytime in the near future. I single top of the line FOX-XP system that can handle 18 wafers simultaneously goes for over $25M (I believe that’s without the automated aligner). It’s not unusual for them to receive orders for a few million to replace consumables. As few as 10 FOX-XP systems in a year puts their revenue at $250M. That’s without any orders for consumables.

I admit, this sales volume will have to be driven by the growth in demand for SiC chips, at least initially. The follow on demand for GaN will possibly come in 2 -3 years, maybe sooner. I’m pretty sure I read somewhere that Nvidia is already selling integrated modules that utilize photonics (or maybe just has a few prototypes, I’m not sure?). In any case, it’s coming, maybe sooner than we think.

Although I do have to agree that this is a bet on the future. And while the razor/blade model is pretty good, it’s not the same as the ARR that comes with the SaaS subscription model.

All in all, I am in the mode of reassessing my investment in Aehr. I’m reluctant to sell any soon after Friday’s meltdown, in fact I bought more on Friday morning which was already profitable by the close. I think the market will see the stock as being on sale right now, so I think it will go higher in the near future.

But it may make sense to trim the stock to free up cash for other investments and buy Aehr leaps. But options is not an appropriate subject for this board, so I won’t say more about it.

@XMFBreakerTinker thanks for confirming what I just wrote on a different Aehr thread. Yes absolutely, the need for burn in testing is driven by the need to weed out infant mortality, it has little to do with the power handling requirements of the end application.

As I understand it, making SiC at the purity level required for ICs is simply very hard to do. I think this also holds true for GaN. The distribution of impurities in SiC and GaN wafers is significantly higher than Si wafers. This makes it economically viable to weed out the chips that are prone to fail in the first 12 - 18 months of service. The yield per wafer is considerably lower than the yield for Si wafers.

I think this is why Aehr will continue to have a difficult time breaking into the memory chip market. All chips, no matter what the substrate still need to undergo functional testing as a fully assembled packaged part. I speculate that it’s economically beneficial to perform the burn in for Si chips once the etched silicon is packaged because there’s just not a high loss rate from burn in. May as well postpone testing to weed out infant mortality as functional testing will have to be performed regardless. It probably makes sense to do all the testing at the part level.


I do not know all the technicalities as to why DRAM would go to AEHR but it may for the same reason that silicon photonics is looking at burn in testing of wafers and AEHR, and that is because the cost of each silicon photonic system is quite large. $10k or more a chip. Thus the failure of a single chip has outsize expense and destroys the whole system. The chip fails, the system fails, and you have to throw it all out.

With DRAM, and it keeps getting higher speeds, it is becoming packaged with more and more expensive GPUs. I don’t know the exact numbers but I am reading a lot of DRAM being packaged in the system, something like 48, 64, or more DRAM in each GPU system. One bad DRAM brings down the whole very expensive system. You put that together with the tens of thousands of these GPUs being used together, the whole AI system fails until you weed out the bad DRAM and replace it with whole new GPU component package because one bad DRAM kills the whole package.

Say you get 1% infant mortality. For SiC that means, with 48 SiC chips in an inverter, is that you are almost assured to have 1 bad SiC chips in every 3 inverters, and likely one in every 2. The SiC chip goes down the whole inverter goes down. So you have electric cars breaking down within a year or two at a rate of 1 to 3 every 3 at best case scenario.

Silicon DRAM has a smaller infant mortality rate one would think. say it is 1 in 1000 (so 10x better than SiC, bit better actually as SiC is worse than 1 in 100 by a little bit anyways). Even at 1 in 1000 you can run the math and see that far too many packaged components using GPUs, as the modern AI example, or with silicon photonics, will suffer from infant mortality and just stop workin in 3 months to 2 years, taking down whole systems with it. Thus the need to infant mortality test.

The problems are two fold (1) to cost effectively test at volume, and (2) to test without actually damaging the increasingly more fragile (as thinner and using more voltage per surface area) chips that can happen with status quo testing equipment but AEHR indicates their system can test at these higher power levels that are being demanded as higher reliability becomes more important without damaging the underlying chip.

So somewhere in there is where the opening for DRAM is for AEHR. The opening for silicon photonics is a simpler straight line and thus why it is already a thing that AEHR has a foothold in but waiting for the silicon photonics product category to take off.


Here is a recent article on how testing is getting higher powered and existing test equipment having difficulty with it:,up%20or%20down%20as%20needed.

Thus, why AEHR thinks it has a role to play in the market. The need for higher powered testing without damaging the chips is also becoming a silicon problem that existing solutions are not handling well.