JabbokRiver and others - I too have been carefully following Gayn’s commnets about silicon memory - - I might be able to add some light to the topic of Aehr’s future potential to begin wafer-level burn-in and test for silicon memory ICs and possibly other high volume silicon integrated circuits. From my past experience (25 yrs in various roles in IC manufacturing w/various companies), and reading a bit into Gayn’s comments in the current and just prior earnings call, I glean the following - -
- The shift underway to improve data transfer speed is driving the need to complex packaging, housing a few to very many chips in ONE package. Since the failure rate of the final package is the product of the failure rate of each individual chip in that package, all of the chips must be stress tested (burned-in under high temp/high voltage conditions) so that each and every chip gets past its early life failure potential. This means that Aehr might see customers wanting to do wafer level stress testing of logic ICs, processor ICs, etc and not just memory - and Gayn has spoken to this tangentially several times.
- Memory ICs are routinely stress tested now (again, burned-in for 12 or more hours under high temp/high voltage conds. to eliminate early life failures that would be expected from a non-stress tested IC over its about 1st 3 months of usage). With a little help from chatGPT - “Yes, most manufacturers of silicon memory Integrated Circuits (ICs) routinely perform burn-in stress testing before shipping out the memory ICs. Burn-in testing is a standard and essential part of the quality assurance process in semiconductor manufacturing. It helps identify and eliminate early failures in the ICs, ensuring their reliability and performance over their intended lifespan.” So the KEY issue re Aehr is whether they can convince the memory makers that their automated/high volume/wafer-level testing results in higher throughput, lower-cost stress testing per chip than the method that the memory maker is currently using to do his stress test today. Personally, I don’t think there is any contest. Individual packaged-part memory testing is slow and costly because the automation is limited. If one could test hundreds-to-thousands of chips at once (ie whole wafer test), and multiple wafers at one time, and in an automated wafer handling manner, ie Aehr’s way, then the cost of stress testing per memory ICs ought to be dramatically lower. This is why I think Gayn said he was smiling (from prior 4q23 CC) - -
"Larry Chlebina
Yeah, I’m there. Gayn, you started to answer my question, my primary question, when you might have an evaluation tool to since you have a fully automated machine now, it seems like one of these memory guys might be interested in evaluating it for future fabs?
Gayn Erickson
I agree. If I were a memory guy, I would want to evaluate our tool as well. So that is something that is important to us. I often tell people, be careful, don’t assume, we’re going to be having revenue anytime immediately, but it is absolutely something that we are that we’re working towards.
And for sure, our new WaferPak automated Aligner is a key piece of that. And we did get feedback from multiple memory companies on that configuration and its capability. I will share that with you. So I’m very for people that know me or have seen the picture of me smiling next to it before we shipped the first one. It’s a passionate project for me and this team is very, very proud of that. So I’ll leave it at that, Larry."
So, in short sum, maybe there’s opportunities for addn’tl sales for Aehr for testing the silicon chips that go into multi-chip modules and for testing silicon memory chips - and that’s a very, very large number of wafers.
Best to all - - JK