But I’m anxious about their ability to hold on to capacity on good enough nodes now that TSMC is the foundry that everyone thinks they must have.
I ended up LoL even if it is not such a laughing matter. Many years ago (in the early 1960s) I figured out that there was a certain combination of talents that made the person who had them immune to suicide. The biggest part is getting sucked in by puzzles. A very good example comes from the world of contract bridge. If you are declarer when dummy comes down, what do you do first? If you try to figure out, now that you can see half the deck, how to make the contract? You are probably safe from (computer science job-related) suicide. If you count dummy’s points (and trumps) and try to decide where partner fouled up in the bidding? Why? Let me explain the imagined situation that had me laughing.
Digression you probably want to skip if you are not a programmer.
You show up for work and someone calls a meeting of all the IT development staff. Let’s say the meeting is called by the VP of R&D. The titles don’t matter, the situation does. In the meeting, the VP says that he just concluded a deal for fifty thousand N5 wafer starts at TSMC a year from today. I need you, people, to take our existing designs and compile them against TSMCs design rules. I’d like a rough report on progress by CoB the day after tomorrow.
I know of one case where this basic situation occurred, and it involved Intel. I happened to be there for job interviews and went out to lunch with the compiler development team. I was told that before my plane landed in Boston, they had already had a meeting with venture capital people. What had happened? There was an oversight in the i432 design. Doesn’t matter now who made the error, and since it was overlooking a necessary operation, anyone could have twigged to it in time to avert disaster.
The i432 chip was a capability machine. One hardware-defined node held a list of top-level capabilities. I won’t go into the mechanism for quickly matching a capability to the request in hand. The problem was, the instruction for adding a capability to a list didn’t work on the hardware-defined root capability. (It added capabilities at the front of the list. Oops!) The software developers had kludged it to treat the second-level capabilities as root capabilities. Only added 5 microseconds to the execution of each instruction. To anyone with a few brain cells to rub together, manufacturing (and demonstrating) that as the first version of the iapx432 was a seriously bad idea. Within a few weeks, Rational had been founded and, in addition to some hardware engineers, everyone I interviewed with–and told me not to take the job–was gone. (Rational was later purchased by IBM, and AFAIK some of the software tools Rational developed are still being sold and supported.)
Strange as it may seem, a company in England sold 432 based systems for the job they were originally intended for–provable code for safety-critical systems. The company is still in business and providing safety-critical code, but apparently not on any Intel hardware. The long-term result of that is that the Ada compiler which is part of GCC will also compile–and prove–safety-critical code. The safety-critical version of Ada is either referred to as SPARK or as the Ravenscar profile.*
Back to TSMC design rules.
Design rules are almost always today implemented by using software from Cadence Design Systems or one of a half-dozen other companies. If you are going to modify a chip design so it meets the design rules, the first step is to have the design description in the proper language for the tools that TSMC uses. (You don’t even want to think about a case where TSMC updates the design rules, and you suddenly have to port them to a different software chain.) If you have your design in Cadence Assura or Pegasus, and you run it against TSMC’s design rules, how many messages about missing some rule’s requirements do you expect? An estimate to the nearest billion will do. 
I hope you didn’t start a print job. The way you do it is to start with a key, but the small, area of the design and run it through the validation tool. In a week or three, when you have that section reporting no errors, try again with a nearby section. Eventually, you hope to have those sections fit together like puzzle pieces. Of course, that process will introduce new errors. Doing this when you are starting with a design that already complies with TSMC design rules at a larger scale can be (relatively) painless if the new rules for the new node are less strict or even just as strict proportionally as for the previous node.
Trying to do this with a design made according to (non-TSMC) design rules is going to be painful and take years. Note that I just slipped a nasty in here. I started with a design using some other software, conversion is going to be painful but doable. Now, we have the software compatibility issue out of the way, and we are at the real test. You need to modify the design so it will work with the new design rules. There are tools, for example, to deal with shrinking a fan-out of three or more down to two. You will also have to deal with timing constraints. An adder or multiplication unit that doesn’t finish in time or at least has the right output bits, even if there is some computation still going on. (An example might be that the status flags could be correct later than the addition or multiplication.)
For some chips, starting from a blank sheet of paper might be the fastest path to a usable design. By then TSMC will have doubled its high-end production capacity. So the only potential risk is a company already using TSMC as a fab. Would TSMC ditch AMD if Intel asked them to? The image that brings to mind is sleeping in a cage with a hungry tiger.
- Contrary to popular opinion, the Ravenscar profile doesn’t forbid exceptions. But it must be documented which handler will handle the reception, and there should be a separate test for it. For example, if a telephone line or other remote connection is broken, an exception is the cleanest model for dealing with it. But you will need to demonstrate that the break that caused the exception will not result in a blockage of any other tasks. Think about a line being dropped in the middle of committing a transaction. (Shudder for a second then move on.) I’m not asking you to implement it, and Ravenscar or SPARK will help a lot. Ada exceptions are carefully designed to make it easy to handle such exceptions cleanly, including canceling other tasks if necessary. (Can you tell that I loved working on language design.
