How MCR Memory Can More Than Double HPC And AI Performance

“Multiplexer combined rank” memory to give the latest Xeons a performance uplift vs. conventional DDR5…

it simultaneously operates both ranks of DDR5 memory to deliver 128 bytes to a CPU (64 bytes from each rank). This means the CPU can perform burst operations at a rate greater than that of a conventional DDR5 RDIMM, realizing potentially greater than 1.5 TB/sec of memory bandwidth capability in a two-socket system. The higher bandwidth is realized by operating the CPU to MRDIMM interface at 2X the DRAM speed, with each DRAM rank able to send or receive data in each cycle. This in addition to offering CPUs with up to 12 channels of memory and a host of Intel Xeon architecture improvements — many of which provide greater numbers of outstanding memory requests and prefetch capabilities ­­– increase performance.
The newest Intel Xeon processors (codenamed Granite Rapids) will support very high core counts with the new technology providing 1S-8S scalability and up to 2 RDIMMS or MRDIMMs per channel.

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It looks like Turin will also support this memory standard.
Alan

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