AMD Shoots Down EPYC Genoa Memory Bug Claims, Says Update On Track

There were persistent rumors circulating on the internet about Genoa having major problems with 2 DIMMS per channel support - implication of a need for major redesign

The following clarification from AMD removes the confusion and states that problems have been resolved


I dunno… I am not sure anybody was saying “major” bug. It is clear that the product as released in November did not support 2 Dimm per channel, and only by the end of Q1 2023 will it. It sounds like the they will slow down the memory access to DDR5-4000 to enable the 2 Dimm’s per channel on the original Genoa design. I suspect there will be a future genoa stepping that allows faster DDR5 speeds. Only now is one vendor releasing a board that allows 2 per channel.

It did sound like Papermaster was caught by surprise with the question and left a less than great answer. It is good that AMD has clarified the situation.

In related news, Intel has 450 design wins for Sapphire Rapids, and shipping into 200 of those now.

I am really disappointed in the general execution of most of these companies now. TSMC has slipped N3 quite a bit, and recently slipped N2 two years. AMD slipped Genoa at least six months to include CXL and hit the November 2022 date, but with crippled silicon. Intel has been a disaster with their product and process schedules. I think between complexity, and competitive pressure they are all over committing to the market.


I have been hearing about INTC SPR design wins, but to me it does not inspire confidence because had these wins been material to share, their public posture on datacenters would have been more enthusiastic (ala client).
I am long both AMD and INTC – hoping that generative AI will be the next killer app for compute that will lift all boats