Samsung and Applied Materials on 3 nm processes…

A word to the wise, if you are interested in the topic definitely don’t skip the comments–they seem to have more information than the article.

For those who want the “drive-by” story, Samsung’s announcement indicates that 3 nm will show up first in low-power and DRAM parts. AMD almost certainly won’t use TSMC’s N3 process for Zen 5. They may use the same process as for Zen 4 or a “4 nm” process which is derived from N5. Why stay off the bleeding edge? That it is the bleeding edge might be a good reason. :wink: But Zen 4 is starting (volume) production, and AMD won’t want to wait while 3 nm design rules are determined.

Intel on the other hand is trying to push ahead at one generation per process node. I think they will be (or are) satisfied with the migration to Intel 7 (Raptor Lake, Granite Rapids) but they have pushed Intel 3 out to 1H2024, and Intel 4 is apparently out of the server picture entirely. Intel has announced an additional server generation Emerald Rapids in 2023, but it will be on Intel 7. That’s almost a detail. Intel 4 will be used for Meteor Lake in 2023. The only remaining product on Intel 20A is Arrow Lake currently scheduled for 2024. Intel has weasel-worded Arrow Lake–or they may just be trying to highlight finally moving to a tiled architecture. In any case, some chiplets in Arrow Lake are expected to be manufactured using Intel 20A. Could they be thinking like AMD that the I/O parts of the chip might as well be manufactured on an earlier process.

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Intel has weasel-worded Arrow Lake–or they may just be trying to highlight finally moving to a tiled architecture.
Meteor lake is the first tiled client product. Sapphire rapids on Intel 7 (now shipping) and Ponte Vecchio GPU (now sampling) are both tiled products as well.
Rumor has it the GPU tile on Meteor lake is TSMC N3, but I counter predict that it will be the ARC 3xx GPU built on TSMC N6. We will see in a few months. The pictures of Meteor lake show four tiles, which is a bit of mystery. One is likely an I/O tile built on an older generation, but the fourth tile is unknown.

In terms of process technology,
Samsung is the first company building GAA (gate all around), but yields are rumored as very low. Samsung N3 will be GAA.
Originally, TSMC N3 was GAA but that program failed and they backed off to finfets with GAA planned for N2 now.
Intel N2 (20A) is planned for GAA, but Intel also has a finfet version they are building as a contingency.


knowing you are also a contributor to the Intel forum, I appreciate the balance you bring to this board regarding intel and what they are doing vs what AMD is doing. Thanks. I always appreciate the technical breakdown Robert brings even if I don’t understand the technical jargon…doc