…is not what Intel is doing, just how the investment community sees the situation. Sapphire Rapids for servers this year, Emerald Rapids next year, and Granite Rapids in 2024. (Emerald Rapids makes a nice contrast in names to Sapphire Rapids, why not Ruby Rapids next?) The problem is that Granite Rapids, in 2024, will be the first EUV server part from Intel to use EUV.
Compare to AMD, where Genoa made with TSMC’s 5 nm* EUV process is shipping soon, pictures here: https://wccftech.com/another-amd-epyc-genoa-zen-4-cpu-leaks-… I don’t know when this year Genoa will ship. AMD has said 2H2022, but along with Raphael the Zen 4 desktop part, the real dates are pretty much out of AMD’s hands. Zen 4 and DDR5 need new sockets (AM5 and SP5) and new motherboards. The availability of motherboards seems, more than anything else, to be the gating factor in when Zen 5 will start shipping for revenue.
- Or is it 5 nm+? To make a long story short, TSMC’s 7 nm process, when announced had a 0.027 µm-squared SRAM density. TSMC’s 5 nm process, when announced had a 0.021 µm-squared SRAM density. Since AMD’s Zen dies are mostly SRAM, a 22% reduction in size meant AMD was in no rush to move to 5nm, especially if processes derived from 7P reduced the SRAM size. Last year TSMC announced their 4nm process, which is derived from the 5nm process: https://fuse.wikichip.org/news/6439/tsmc-extends-its-5nm-fam… Along the way, 5PP (5+) disappeared from roadmaps.
I’m tempted to get out a ruler and measure pictures of Zen 3, Zen 3+, and Zen 4 to figure out the actual SRAM cell sizes. But not right now. Since Zen 4 wavered between 5 nm and 5+ nm on roadmaps, I suspect that TSMC folded smaller SRAM from 5PP into 5P and eliminated the separate process.