Cowos Capacity
From a strategic perspective, advanced packaging is becoming incredibly important and the main driver behind the Foundry 2.0 Strategy
Even though TSMC is adding as much advanced packaging technology as possible, it is nowhere near fulfilling the demand. TSMC expect to grow capacity by 60% CAGR but will not be able to meet demand before sometime during 2026 at best.
Margins have been low but are improving to a level close to corporate average margin as yields improve. CoWoS is the main reason that TSMC is changing its strategy to 2.0. All of the HPC customers will need advanced packaging to integrate High Bandwidth memory on an interposer. Later on this will be a need for PC processors and everything else AI.
The new 2.0 Foundry Strategy:
While the Foundry 2.0 strategy looks like a market expansion strategy from the $125B (2023) Foundry markets to add the packaging market of $135B bringing the total addressable market for TSMC to $250B. This changes TSMC’s market share from 55.3% to 28% in the new definition.
Apart from market expansion, Foundry 2.0 also aligns closely with the changed need of the top HPC customers, Apple, Nvidia, Intel, AMD and Broadcom. TMSC can basically deliver everything but the memory element of the CPU and GPU boards.
From a technology perspective, the move makes TSMC less dependent of the continuation of Moore’s law predicting continously smaller 2D geometries as the advanced packaging effectively opens up for 3D integration and technology advancement.
It represents the transformation of TSMC from a components company to a subsystems company, just like Nvidia’s transformation from GPU to AI Server boards.
As Nvidia developed Blackwell, it became obvious that the silicon for the GPU itself got diluted. The introduction of more memory, Silicon interposers and large slabs of advanced substrates, made the GPU share of the BOM decline. The Foundry 2.0 strategy is also aimed at controlling more of the supply chain in order to maintain TSMC’s importance as supplier to the CPU and GPU customers.
The capital allocation strategy, reveals the current fiscal importance of each of the main areas of TSMC business. If we didn’t know it, TSMC is still an advanced logic node company and that will continue. The new advance packaging, test and mass making (assembly??) will be allocated 10% of the total CapEx budget which is 31B$ in 2024.
While this sounds modest, the capital requirements for the Test and Packaging (OSAT) companies is a lot less than for semiconductor manufacturing. The largest OSAT companies are ASE and Amkor and they have CapEx spend of and estimated 2.5B$ in 2024. TSMC is dead serious about entering this industry and the established companies need to be on their toes.
In strange but true additional news: Intel IFS may also be providing NVIDIA with Foveros (similar to TSMC COWOS) packaging capacity:
Alan
I’m not sure I understand what is meant by packaging. So why it so difficult and important?
Thanks in advance for any education.
There is a difference between “packaging”, and “advanced packaging”. The original chiplet EPYC was basic old “packaging”. OTOH, all the modern AI accelerators and many new client and server products use “advanced packaging”. If you want the buzzwords, you can read up on Cowos from TSMC, or EMIB/Foveros from INTC. In a nutshell, you need all new assembly tooling to do “advanced packaging” and while the industry is building and installing tools as quickly as they can, the demand continues to outpace supply.
The advantage of “advanced packaging” is it is a much higher speed interconnect at much lower power consumption than conventional methods.
About packaging: see
Understanding CoWoS Packaging Technology
In order to cater to the computing demands for high performance computing (HPC) and artificial intelligence (AI), a need for a scalable package was felt. Chip-on-wafer-on-substrate (CoWoS) refers to the advanced packaging technology that offers the advantage of a larger package size and more I/O connections. It allows 2.5D and 3D stacking of components to enable homogenous and heterogenous integration. Previous systems faced memory limitations and contemporary data centers employ the use of high bandwidth memory (HBM) to enhance memory capacity and the bandwidth. CoWoS technology allows heterogenous integration of logic SoC and HBM on the same IC platform.
Photo inspiration: TSMC
CoWoS Package Overview
CoWoS architecture encompasses both 2.5D horizontal stacking and 3D vertical stacking configurations, revolutionizing the traditional paradigm of chip packaging. This innovative approach allows for the stacking of various processor and memory modules layer by layer, creating chiplets that are interconnected to form a cohesive system. By leveraging through-silicon vias (TSVs) and micro-bumps, CoWoS facilitates shorter interconnect lengths, reduced power consumption, and enhanced signal integrity compared to conventional 2D packaging methodologies.
In practical terms, CoWoS technology enables the seamless integration of advanced processing units, such as GPUs and AI accelerators, with high-bandwidth memory (HBM) modules. This integration is particularly crucial for AI applications, where massive computational power and rapid data access are paramount. By colocating processing and memory elements within close proximity, CoWoS minimizes latency and maximizes throughput, thereby unlocking unprecedented performance gains for memory-intensive tasks.
Another link Chip-on-Wafer-on-Substrate (CoWoS) - TSMC - WikiChip
Thanks for those explanations. I think the last build I has was a Zen 3 with no AI and a GPU used for nothing much.