Universal Chiplet Interface


When the hyperscalers, the major datacenter compute engine suppliers, and the three remaining foundries with advanced node manufacturing capabilities launch a standard together on Day One, this is an unusual, significant, and pleasant surprise. And this is precisely what has happened with Universal Chiplet Interconnect Express.

The PCI-Express interconnect standard and its predecessors have defined how peripherals hook into compute complexes for decades, and thankfully after a long drought of seven years getting to 16 Gb/sec data rates with PCI-Express 4.0, which spec’d out in early 2017 and first appeared in systems in late 2018, the PCI-Express standard looks like it can carry us to the end of the decade with a doubling of bandwidth every two years. This, of course, is a cadence that matches the Moore’s Law improvements in transistor density and throughput for compute engines of all kinds, which is why it is natural enough to look inwards and start using PCI-Express as the basis of a chiplet interconnect.

That, in short, is precisely what UCI-Express is going to attempt to do, and not a moment too soon with every compute and networking chip vendor looking at 2D, 2.5D, and 3D chiplet architectures as they snap their chips into pieces to make them more manufacturable at an economic cost as Moore’s Law slows down but performance and throughput demands on compute and networking devices rising faster than the thermal envelopes.

It is no surprise to us at all that the UCI-Express protocol is coming out of Intel’s Beaverton, Oregon facility and that Das Sharma is driving it and the author of the whitepaper describing its goals. And given that Intel Foundry Services wants to open itself up to manufacturing all kinds of chippery and the packages (direct ball grid array mounted or socket) that wrap around them, it is no surprise, either, that Intel wants an open chiplet standard. This will be a necessary condition for the mass customization and co-design that is going to be necessary for all kinds of compute and networking as Moore’s Law transistor densities increase but the cost per transistor does not necessarily go down.

Moving to chiplets is a way to help lower the manufacturing costs and increase the yields on packages, but there is an increasing cost in package manufacturing and more complex testing and validation. It would be interesting to see the data for the above broken out by monolithic and chiplet designs.

As Das Sharma points out in the whitepaper, UCI-Express is not just about having the ability to mix and match chiplets with different designs from different designers, which is a powerful concept indeed. (Imagine being able to make a package with a baby Xilinx programmable logic block, a set of AMD Epyc compute blocks, Intel CXL memory and I/O interconnect, and Nvidia GPU chiplets?) The other key driver of the UCI-Express standard – and why it needs to be a standard – is to create well-defined die-to-die standards and testing and validation procedures that mean mixed-and-matched chips work when they are assembled into a 2D socket complex or a 2.5D interposer complex.

It is interesting to contemplate how UCI-Express will allow components of the server motherboard of today to be brought down into the package or socket of tomorrow as well as being used to interconnect compute and networking elements inside of that package or socket. And with the addition of a UCI-Express switch – why not? – either on the package or on the motherboard, there are all kinds of interesting, fine-grained interconnect possibilities that could span several racks and with optical links could span rows in a datacenter. Imagine if any element within a compute complex to talk directly over a PCI-Express fabric in a few hops to any other element within a pod of gear, without InfiniBand or Ethernet with RDMA? Just get rid of it all, and talk directly. This is why we have said that PCI-Express is the unintended by formidable datacenter interconnect and that across a datacenter with the need for peer-to-peer links to all kinds of components, PCI-Express fabrics will be pervasive.

This is a big deal.


What I missed in the above: the companies participating.

Perhaps the most interesting thing about UCI-Express, as we said at the beginning of this story, is the group of companies that are supporting it – meaning are behind the effort to help steer it, not that have products that are making use of it or have committed publicly to using it. As for foundries, we have Intel, Taiwan Semiconductor Manufacturing Co, and Samsung behind it, which is all of the advanced foundry that there is on Earth. In the hyperscaler and cloud builder camps, we have Google, Meta Platforms, and Microsoft, which is well over half of the cloud/hyperscale capacity on Earth. Among chip designers, we have AMD, Arm Holdings, Intel, Samsung, Qualcomm, and possibly Microsoft if it is indeed working on its own Arm server chips as many suspect. Advanced Semiconductor Manufacturing, a Taiwanese provider of assembly and test services for chip complexes, is also on board. The founding companies are finalizing the incorporation of the UCI-Express standards body, appointing a governance board, and then get to work defining the chiplet form factor, management, enhanced security, and protocol stacks for UCI-Express. It is not clear how any of the companies above will implement UCI-Express, and when it might replace proprietary technologies.

That is a pretty big first day push, and the only notable absences that matter are Nvidia and, to a much lesser but still important extent, IBM. Time will tell if Big Green and Big Blue come around. And for that matter, Amazon Web Services, Alibaba, Baidu, and Tencent are important and will probably play along because they stand to benefit from an industry standard, too.

In a related note on packaging capital spending:
Intel is the top investor, with $3.5 billion.
The other leader, TSMC, is following through with $3.05 billion of CapEx.
The industry is betting big on chiplets.

In unrelated news Intel presented at Morgan Stanley:

The only tidbit I found interesting is Gelsinger is personally doing a weekly review of the Intel 4, 3, 20A, and 18A yields…

The only tidbit I found interesting is Gelsinger is personally doing a weekly review of the Intel 4, 3, 20A, and 18A yields…

The entire survival of his company as a relevant player depends on them and they are far from guaranteed to be smashingly great. If he’s not looking at them very regularly he’s not doing his job. Especially with shifting to foundry as a business.

IFS makes IDM better, IDM makes IFS better. What do I mean when I say that? The integrated design to manufacturing, it was always fairly proprietary internally. Well, when I become a foundry, I’m no longer proprietary. Industry PDKs, industry design tools it’s forcing us to fully leverage and align with those industry standards. It also forces a daily benchmarking, I mean I have foundry customers who are testing Intel 3, Intel 18A every day.

They’re telling us, well, on this parameter, on this corner, I think I get better characteristics on a competitor’s process technology, I mean we’re getting that kind of feedback every day to make us better. And the engagement, [indiscernible] from the CAD tool providers, wow, this is a different Intel. We’re engaging and how to go make this better?

But IFS also benefits from IDM, essentially, they get $10 billion of free R&D, LTD, oh, it’s all available to them. All of the IP libraries, design flows, we’re making those all available to foundry customers. So it really drives the synergy of both sides of the business.

The last 15 years have been dominated by the geopolitics around where the oil reserves are. Every aspect of your life is going digital. Everything digital needs semiconductors. Where the fabs are is more important than where the oil reserves have been. It is that critical, and that’s why you’re seeing nations come behind in a very fundamental way. We need rebalanced supply chains. And that’s why I made the statement at the Investor Day, a bet on Intel is a hedge of the world geopolitics.

Is that important? And that’s why you’re seeing U.S. and Europe come behind us in a very substantial way to say, absolutely, we’re going to help to capitalize the build-outs of foundry. We got the RAMP-C program as essentially, they’re paying us to build a government foundry right now. We’re seeing the early engagement of the foundry customers in a very positive way.

On a side note: I’m sure China is watching how the world has snapped back from Russia, and weighing what that might suggest about any plan to go after Taiwan. Could be they would be concerned similar economic isolation – but they are too wired into the world economy in a way Russia is not. Hard to cut them off since they actually make most things. :confused: Could be they’d think this is just the moment to do something-- the world is busy responding to Russia. Could be one reason NATO is holding off on certain kinds of engagement with Russia is they are worried about the other global shoe dropping. Who knows? I should be working for a living, let me go do that…

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The entire survival of his company as a relevant player depends on them
To some extent… but it seems a little early to be tracking 18A yields, which is a 2024/2025 technology. Then again, based on other comments about foundry it appears Intel 18A is already yielding which is something.