Paradigm shift: 3D chip assembly

https://www.wsj.com/articles/chiplet-amd-intel-apple-asml-mi…

**The Microchip Era Is Giving Way to the Megachip Age**
**To continue making our gadgets more powerful, engineers have worked out a new way to get around the barriers to making microchips faster: Just make them bigger.**
**By Christopher Mims, The Wall Street Journal, July 30, 2022**

**...**
**One way engineers are making this happen is by piling microchips atop one another. It’s like urban infill, only instead of building towering new apartment blocks, the usually pancake-flat tiles of silicon inside of computers are becoming multistory, with the circuitry used for functions such as memory, power management and graphics stacked on top of each other....**

**This is now possible in large part because of recent innovation in an area that has long been neglected by the chip industry. That area is “packaging.” That’s the usually obscure step that comes after a microchip has been manufactured, when it is connected to tiny wires and enveloped in plastic before being placed on a board, also covered in wires, that connects it to the rest of a device....The new packaging of megachips instead connects two chips — and potentially many more — directly, instead of using a bus....**

**The essential building block to make megachips and chip stacking happen is a new kind of microchip, called a “chiplet.” It does away with some of the old-style circuitry to communicate more directly with other chiplets. By creating many short, direct connections — often forged from the same silicon that the chips themselves are made from, rather than copper or some other metal — these chiplets can be fused with other chiplets to form megachips....** [end quote]

The big chip manufacturers, including Intel, TSMC, Samsung and AMD, are cooperating on a new standard, called the Universal Chiplet Interconnect Express, or UCIe.

The paradigm shift toward 3D chip stacking and universal chiplet design is bound to lead to innovations in the future.

Wendy

15 Likes

3D chips have been talked about for decades. The engineering technology to make it happen is what has been missing. Heat dissipation might be a problem.

The Captain

2 Likes

There are a few challenges beside the “ability” that I can see, Captain’s point about getting rid of the heat buildup is non-trivial. The packaging is generally (by definition) non-conductive and the general rule is that the faster/more chips are in a package the hotter it gets, so either the chips have to become more robust or there has to be a way to quickly dump a load of heat.

Also, the more functionality in a package, unless it is extremely programable and “malleable”, the less flexible it becomes. Sure, there are enough PC’s being made to package all the required functions into a single chip, but then there are those who want a different graphics ability, sound ability and so on from what is packages, so much of the chip is wasted. That said, the economy of scale in making a single design and just “turning on” what’s ordered could be a huge saving (as long as handling the excess heat and power usage is a good trade-off.

I have a feeling that the “powers that be” are trying to move us (collectively) on the consumer and small business level to a thin-client, cloud-based, model where our personal device (PC, Phone, whatever) no longer needs a huge amount of power, memory and storage as we will be “renting” it from a third party. Places like Google, Amazon, Apple and Microsoft have huge cooling issues and anything which packages chips in a more efficient (smaller) package can have large benefits in their server farms.

Jeff

4 Likes

How much power will these consume? Will a single circuit in the home be able to power one of these?

<How much power will these consume? Will a single circuit in the home be able to power one of these? >

From the article:
“But these megachips can present engineers with challenges when it comes to managing the extra heat they create from all the calculations being performed in densely-packed circuits. And though they can be more energy efficient, their sheer size means they sometimes end up using a lot of power, too. Intel’s Ponte Vecchio chip, for example, is efficient on a per-calculation basis, but consumes 600 watts, nearly enough to run a hair dryer. If you are wondering why megachips aren’t yet in your mobile device, this is your answer.”

Wendy

but consumes 600 watts, nearly enough to run a hair dryer.


An alternative way to look at this is that it gives off the same amount of heat as the hair dryer
That was one of my pet peeves about my new PC. On one hand I’m saving power by using solid state drives instead of hard disks and on the other, my “gaming class” graphics board with its 6GB of ram has enough heatsinks and fans mounted on it to more than make up the difference.

Jeff

1 Like

but consumes 600 watts, nearly enough to run a hair dryer.

================================================

Another way to help heat your home on winter nights or help your hot water heater stay hot.
:grinning:
Jaak

On a tech podcast I listen to they have been talking about computers that draw so much current they have to be plugged into two outlets.

The paradigm shift toward 3D chip stacking and universal chiplet design is bound to lead to innovations in the future.

True. But also innovations in the past.

There have been various 3D chip stacking “experiments” going back a few decades.
The industry has been shipping high production volumes of 3D stacked memory for almost 10 years.
This has been inside GPUs and in server memory chips, primarily.

See here: https://en.wikipedia.org/wiki/High_Bandwidth_Memory

And chiplet technology has been shipping for 3 or 4 years in AMD’s server processors.

What is new here is the standardization of the chiplet to chiplet communications interface. This would potentially allow a device to be designed to contain chiplets from different companies, similar to how a single circuit board can contain chips from different companies.

In servers this probably means higher performance and the massive power being discussed.
But in other products it may just reduce power (less power needed to communicate between chips) and reduce area/size (chiplets can be closer together than chips on a board).

Mike