Micron using Epyc for design software


Micron Technology is now using AMD’s newly announced third-generation Epyc server CPUs to power most of its high-demand applications for designing memory and storage chips.

Ram Peddibhotla, AMD’s corporate vice president of Epyc product management, told The Register last week about Micron’s decision, and a spokesperson for Micron later confirmed to us that it moved “most of its most demanding” electronic design automation applications to servers with AMD’s CPUs last year.

“They have a state-of-the-art, high performance architecture for EDA to get them to design their products [and] maximize productivity for their designers,” he said.

This allowed Micron to improve EDA performance by 30 percent, and it also lowered the combined upfront and ongoing costs for running datacenters, according to Peddibhotla.

He added that Micron is now testing servers with AMD’s new Epyc “Milan-X” processors — which were officially released on Monday — and found that they provide an additional 40 percent performance boost over last year’s third-gen EPYC chips on select EDA workloads thanks to the CPU’s large 768MB of L3 cache.

“It was really, really good with [AMD’s third-gen Epyc] and getting even better with Milan-X,” he said.

Micron did not say which CPU architecture the company previously used for its EDA datacenters, but what’s notable to us is that the company did not choose Intel’s latest Xeon processors, which is understandable if AMD’s latest performance comparisons are reliable.

Some workloads really love the big cache.



Some workloads really love the big cache.


Some years ago, we were running computer simulations of complex scenarios that really liked gigabytes of main memory. Those scenarios would have run a lot faster still with gigabytes of cache.