This is really about Intel’s technology roadmap, but I figure that anyone who reads the Intel group and is interested in comparative technology reads this group.
You can find a roadmap here: https://www.anandtech.com/show/16823/intel-accelerated-offen… I’m just going to talk about power delivery and interposers.
What you gain from putting the power under the transistors is easy to figure. But using two wafers to manage that is expensive. Right?
What if you have that silicon there for other reasons. AMD Ryzen and EPYC “chips” all depend on an interposer to mount the Zen and I/O chips onto. So why not use that piece of silicon to distribute the power. The bulk of the various chips will serve as the ground plane. It will be necessary to run connections through the interposer to the pins (or non-pins with Zen 4 and later). But that has to be done anyway. Getting power above the transistor layers can be done with plated-through vias. That’s what I’m expecting in Zen 4. AMD could use a third piece of silicon, but I don’t see why.
Now on to Intel. Intel has picked a fancy name, PowerVia for the technology. I figure from Anandtech’s (not Intel’s) graphic that Intel will be using a silicon interposer for the Intel 20A* node. I think they could start earlier, but Intel 4 is supposed to use Foveros 36 micron then EMIB 45 micron, and finally Foveros 25 micron and Foveros Direct both aligned with Intel 3. This puts PowerVia, and by extension “full” interposers in mid to late 2024. Do I believe that Intel will manage three new process nodes in two years? No. Saying more and staying polite? That’s difficult. So I’ll go back to AMD and TSMC for a bit.
Not interested in history skip to the next dashed line.
Going back into history, there have been long process nodes and short nodes. The reasons have little to do with the technology as such. Most companies (without fabs) base their moves from one node to the next based on cost. Period. They may have a new design they want to build, which takes away extra development costs, but say that you can expect 160% (or 60% more) from the next node today. Well, whenever your new design is expected to be running through the fab. If this is a “full node” you expect to get twice as many chips once the learning curve has done some of its work. Call this the normal case.
Sometimes all the capex for the current node can be used at the new node, and yields are expected to approach the present node yield. The old node won’t have much lifetime. A short node.
What if there are serious problems with getting yields above (say) 20%. That will make the current node a long node. In Intel’s recent experience, a very, very long node. (14 nm)
A lot of fab customers looked at the (so-called) 10 nm offerings and saw nothing but trouble. Double-patterning mostly. Double-patterning could be avoided with EUV, but that wasn’t really ready. What AMD and a lot of other companies did was to say, if we have to do double-patterning, jumping to 7 nm instead will cover all those pesky double-patterning costs. So they skipped 10 nm. I could produce lots of guesses as to the comparative costs, but… AMD worked with GF to produce a version of 14 nm with tighter layout macros. They called 12 nm. Whether the name matches anything is irrelevant. What was relevant was that it allowed AMD to make Zen+ parts for less than Zen parts, and with higher yields and clock speeds. (Higher yields? When redesigning the library it makes sense to get rid of the few macros that result in most of the rejects.)
What is really important here is that 7 nm has been a long node, along with TSMC’s named variants. Expect 5 nm to be an even longer node. Whether Zen 5 uses one of TSMC’s 5 nm variants that begins with a 4, or some AMD-only variant. Don’t expect Zen 5 to jump to N3. Way too big a risk. There may be a Zen 6 at the N3 node, or AMD may retire the Zen name. My guess is Zen 4 later this year, Zen 4c as a kicker next year, and Zen 5 in early 2024. Zen 6? Chrystal ball very cloudy, check again–in a year or two.
Could AMD use N3 for Zen 5? Big NO! based on corporate culture. Lisa Su doesn’t like to take risks, and AMD doesn’t need to take any right now. Could AMD design a Zen 6 alongside Zen 5, and Zen 5 have a very short market lifetime? The first part of that is easy. AMD is designing Zen 6 and putting the finishing touches on Zen 5 right now. Everyone in this business knows that you put the gun to your head and pull the trigger. Four years later, you find out if the gun went off.
Since I expect Zen 5 to use the same process, with perhaps a few tweaks, as Zen 4, the second part is that I expect Zen 4 to have a relatively short lifetime. All those things that didn’t go into Zen 4 will get crammed into Zen 5. Some will end up falling off the table, but most will get in. And since Zen 5 in addition to sharing a process with Zen 4 will share most of its detailed design, AMD could (possibly) have it ready to go by January. They won’t release it then, but the point I am making here is that there won’t be much fab work to do (hot lots, etc.) on Zen 5.
- I decided that flagging Intel’s process names in bold is more useful than doing the same for their codenames. There are just too many Intel codenames, and recently they changed too fast. (Not Alder Lake, just everything before that.
