Also, it is Sapphire Rapids, not Lake…
Oops, my bad.
Power Via puts multiple layers of metal on the backside of the wafer to do the power routing. This means that somehow the front side lithography alignment marks are now visible on the backside?
Or you could put some TSVs (vias) through the wafer before litho to provide alignment marks? I don’t know, and I doubt there are all that many people inside Intel that know what it will finally look like.
My speculation was more about AMD using silicon that will be there anyway to route the power. AMD has an advantage right now in that, at least for non-APU Ryzen and EPYC chips, there is only one voltage needed on the CPU chiplets. They may at some point try to run different processors on different voltages, but I suspect that if they do that, it will be on a per chiplet basis. (I’m also expecting that if AMD makes an APU that has both Zen 4 and Zen 4c cores, they will be on separate chiplets.)